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  ? semiconductor components industries, llc, 2006 november, 2006 ? rev. 14 1 publication order number: mc100ept26/d mc100ept26 3.3v1:2 fanout differential lvpecl/lvds to lvttl translator description the mc100ept26 is a 1:2 fanout differential lvpecl/lvds to lvttl translator. because lvpecl (p ositive ecl) or lvds levels are used only +3.3 v and ground ar e required. the small outline 8 ? lead package and the 1:2 fanout design of the ept26 makes it ideal for applications which require the low skew duplication of a signal in a tightly packed pc board. the v bb output allows the ept26 to be used in a single ? ended input mode. in this mode the v bb output is tied to the d0 input for a non ? inverting buffer or the d0 input for an inverting buffer. if used, the v bb pin should be bypassed to ground with > 0.01  f capacitor. for a single ? ended direct connection, use an external voltage reference source such as a resistor divider. do not use v bb for a single ? ended direct connection or port to another device. features ? 1.4 ns typical propagation delay ? maximum frequency > 275 mhz typical ? the 100 series contains temperature compensation ? operating range: v cc = 3.0 v to 3.6 v with gnd = 0 v ? 24 ma ttl outputs ? q outputs will default low with inputs open or at v ee ? v bb output ? pb ? free packages are available *for additional marking information, refer to application note and8002/d. marking diagrams* a = assembly location l = wafer lot y = year w = work week m = date code  = pb ? free package alyw   ka26 so ? 8 d suffix case 751 1 8 tssop ? 8 dt suffix case 948r 1 8 1 8 see detailed ordering and shipping information in the package dimensions sect ion on page 5 of this data sheet. ordering information kpt26 alyw  1 8 http://onsemi.com dfn8 mn suffix case 506aa 3w m   1 4 (note: microdot may be in either location)
mc100ept26 http://onsemi.com 2 1 2 3 45 6 7 8 q0 gnd v cc figure 1. 8 ? lead pinout and logic diagram d q1 d v bb nc lvttl lvpecl (top view) table 1. pin description pin function q0, q1 lvttl outputs d0**, d1** differential lvpecl inputs pair v cc positive supply v bb output reference voltage gnd ground nc no connect ep exposed pad must be connected to a sufficient thermal conduit. electrically connect to the most negative supply or leave floating open. ** pins will default to v cc /2 when left open. table 2. attributes characteristics value internal input pulldown resistor 50 k  internal input pullup resistor 50 k  esd protection human body model machine model charged device model > 1.5 kv > 100 v > 2 kv moisture sensitivity, indefinite time out of drypack (note 1) pb pkg pb ? free pkg so ? 8 tssop ? 8 dfn8 level 1 level 1 level 1 level 1 level 3 level 1 flammability rating oxygen index: 28 to 34 ul 94 v ? 0 @ 0.125 in transistor count 117 devices meets or exceeds jedec spec eia/jesd78 ic latchup test 1. for additional information, see application note and8003/d.
mc100ept26 http://onsemi.com 3 table 3. maximum ratings symbol parameter condition 1 condition 2 rating unit v cc positive power supply gnd = 0 v 3.8 v v in input voltage gnd = 0 v v i  v cc 0 to 3.8 v i bb v bb sink/source 0.5 ma t a operating temperature range ? 40 to +85 c t stg storage temperature range ? 65 to +150 c  ja thermal resistance (junction ? to ? ambient) 0 lfpm 500 lfpm soic ? 8 soic ? 8 190 130 c/w c/w  jc thermal resistance (junction ? to ? case) standard board soic ? 8 41 to 44 c/w  ja thermal resistance (junction ? to ? ambient) 0 lfpm 500 lfpm tssop ? 8 tssop ? 8 185 140 c/w c/w  jc thermal resistance (junction ? to ? case) standard board tssop ? 8 41 to 44 c/w  ja thermal resistance (junction ? to ? ambient) 0 lfpm 500 lfpm dfn8 dfn8 129 84 c/w c/w t sol wave solder pb pb ? free 265 265 c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. table 4. pecl input dc characteristics v cc = 3.3 v; gnd = 0.0 v (note 2) symbol characteristic ? 40 c 25 c 85 c unit min typ max min typ max min typ max v ih input high voltage (single ? ended) 2075 2420 2075 2420 2075 2420 mv v il input low voltage (single ? ended) 1355 1675 1355 1675 1355 1675 mv v bb output voltage reference 1910 2035 2160 1910 2035 2160 1910 2035 2160 v v ihcmr input high voltage common mode range (differential) (note 3) 1.2 3.3 1.2 3.3 1.2 3.3 v i ih input high current 150 150 150  a i il input low current d d ? 150 ? 150 ? 150 ? 150 ? 150 ? 150  a note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 2. input parameters vary 1:1 with v cc . 3. v ihcmr min varies 1:1 with gnd, v ihcmr max varies 1:1 with v cc . the v ihcmr range is referenced to the most positive side of the differential input signal. table 5. ttl output dc characteristics v cc = 3.3 v; gnd = 0.0 v; t a = ? 40 c to 85 c symbol characteristic condition min typ max unit v oh output high voltage i oh = ? 3.0 ma 2.4 v v ol output low voltage i ol = 24 ma 0.5 v i cch power supply current 10 20 18 ma i ccl power supply current 15 28 35 ma i os output short circuit current ? 50 ? 150 ma note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously.
mc100ept26 http://onsemi.com 4 table 6. ac characteristics v cc = 3.0 v to 3.6 v; gnd = 0.0 v (note 4) symbol characteristic ? 40 c 25 c 85 c unit min typ max min typ max min typ max f max maximum frequency (figure 2) 275 350 275 350 275 350 mhz t plh , t phl propagation delay to output differential (note 5) 1.2 1.2 1.5 1.5 2.0 1.8 1.2 1.2 1.5 1.5 2.0 1.8 1.3 1.2 1.7 1.5 2.2 1.8 ns t sk+ + t sk ?? t skpp within device skew++ within device skew ? ? device ? to ? device skew (note 6) 15 20 100 60 85 500 15 20 100 60 85 500 20 30 100 85 85 500 ps t jitter random clock jitter (rms) (figure 2) @  200 mhz @ > 200 mhz 6 20 30 275 6 40 30 275 6 170 30 275 ps v pp input voltage swing (differential configuration) 150 800 1200 150 800 1200 150 800 1200 mv t r t f output rise/fall times (0.8v ? 2.0v) q, q 330 600 950 330 600 950 330 650 950 ps note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 4. measured with a 750 mv 50% duty ? cycle clock source. r l = 500  to gnd and c l = 20 pf to gnd. refer to figure 3. 5. reference (v cc = 3.3 v 5%; gnd = 0 v) 6. skews are measured between outputs under identical transitions. figure 2. typical v oh / jitter versus frequency (25  c) frequency (mhz) v oh (v) 0.0 1.0 2.0 3.0 v oh v ol  0.5 v jitter random clock jitter (ps rms) 12 8 4 0 0 100 200 300
mc100ept26 http://onsemi.com 5 figure 3. ttl output loading used for device evaluation characteristic test c l *r l ac test load gnd *c l includes fixture capacitance application ttl receiver ordering information device package shipping ? mc100ept26d soic ? 8 98 units / rail mc100ept26dg soic ? 8 (pb ? free) 98 units / rail mc100ept26dr2 soic ? 8 2500 / tape & reel mc100ept26dr2g soic ? 8 (pb ? free) 2500 / tape & reel mc100ept26dt tssop ? 8 100 units / rail mc100ept26dtg tssop ? 8 (pb ? free) 100 units / rail mc100ept26dtr2 tssop ? 8 2500 / tape & reel mc100ept26dtr2g tssop ? 8 (pb ? free) 2500 / tape & reel mc100ept26mnr4 dfn8 1000 / tape & reel MC100EPT26MNR4G dfn8 (pb ? free) 1000 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
mc100ept26 http://onsemi.com 6 resource reference of application notes an1405/d ? ecl clock distribution techniques an1406/d ? designing with pecl (ecl at +5.0 v) an1503/d ? eclinps  i/o spice modeling kit an1504/d ? metastability and the eclinps family an1568/d ? interfacing between lvds and ecl an1672/d ? the ecl translator guide and8001/d ? odd number counters design and8002/d ? marking and date codes and8020/d ? termination of ecl logic devices and8066/d ? interfacing with eclinps and8090/d ? ac characteristics of ecl devices
mc100ept26 http://onsemi.com 7 package dimensions soic ? 8 nb case 751 ? 07 issue ah seating plane 1 4 5 8 n j x 45  k notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. 6. 751 ? 01 thru 751 ? 06 are obsolete. new standard is 751 ? 07. a b s d h c 0.10 (0.004) dim a min max min max inches 4.80 5.00 0.189 0.197 millimeters b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.053 0.069 d 0.33 0.51 0.013 0.020 g 1.27 bsc 0.050 bsc h 0.10 0.25 0.004 0.010 j 0.19 0.25 0.007 0.010 k 0.40 1.27 0.016 0.050 m 0 8 0 8 n 0.25 0.50 0.010 0.020 s 5.80 6.20 0.228 0.244 ? x ? ? y ? g m y m 0.25 (0.010) ? z ? y m 0.25 (0.010) z s x s m  1.52 0.060 7.0 0.275 0.6 0.024 1.270 0.050 4.0 0.155  mm inches  scale 6:1 *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint*
mc100ept26 http://onsemi.com 8 package dimensions dim min max min max inches millimeters a 2.90 3.10 0.114 0.122 b 2.90 3.10 0.114 0.122 c 0.80 1.10 0.031 0.043 d 0.05 0.15 0.002 0.006 f 0.40 0.70 0.016 0.028 g 0.65 bsc 0.026 bsc l 4.90 bsc 0.193 bsc m 0 6 0 6  seating plane pin 1 1 4 85 detail e b c d a g detail e f m l 2x l/2 ? u ? s u 0.15 (0.006) t s u 0.15 (0.006) t s u m 0.10 (0.004) v s t 0.10 (0.004) ? t ? ? v ? ? w ? 0.25 (0.010) 8x ref k ident k 0.25 0.40 0.010 0.016 tssop ? 8 dt suffix plastic tssop package case 948r ? 02 issue a notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a does not include mold flash. protrusions or gate burrs. mold flash or gate burrs shall not exceed 0.15 (0.006) per side. 4. dimension b does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.25 (0.010) per side. 5. terminal numbers are shown for reference only. 6. dimension a and b are to be determined at datum plane ?w?.
mc100ept26 http://onsemi.com 9 package dimensions dfn8 case 506aa ? 01 issue d notes: 1. dimensioning and tolerancing per asme y14.5m, 1994 . 2. controlling dimension: millimeters. 3. dimension b applies to plated terminal and is measured between 0.25 and 0.30 mm from terminal. 4. coplanarity applies to the exposed pad as well as the terminals. ??? ??? ??? ??? a d e b c 0.10 pin one 2 x reference 2 x top view side view bottom view a l (a3) d2 e2 c c 0.10 c 0.10 c 0.08 8 x a1 seating plane e/2 e 8 x k note 3 b 8 x 0.10 c 0.05 c a b b dim min max millimeters a 0.80 1.00 a1 0.00 0.05 a3 0.20 ref b 0.20 0.30 d 2.00 bsc d2 1.10 1.30 e 2.00 bsc e2 0.70 0.90 e 0.50 bsc k 0.20 ??? l 0.25 0.35 1 4 8 5 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 mc100ept26/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative eclinps is a trademark of semiconductor components industries, llc (scillc).


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